The integration density of integrated circuit memory devices such as integrated circuit Dynamic Random Access Memories (DRAMs), generally continues to increase. With the increase in integration density, the unit area of each memory cell generally tends to decrease. As is well known to those having skill in the art, integrated circuit DRAM devices include a capacitor for each memory cell. As the unit area per cell is reduced, the capacitance also tends to be reduced. This reduction in capacitance may degrade the performance of the integrated circuit memory. For example, read accuracy may decrease and soft error rates may increase. Also, excessive amounts of power may be required for device operation at low voltage. Accordingly, there is a need to ensure a large enough cell capacitance, notwithstanding the decrease in area of the unit cell in highly integrated memory devices.
There are three general techniques which have been used in attempts to increase the capacitance of a memory cell within a unit cell area. As is well known to those having skill in the art, an integrated circuit capacitor generally includes a lower electrode, an upper electrode and a dielectric layer therebetween. The first technique for increasing capacitance per unit area is to form a thinner dielectric. The second technique is to increase the effective area of the capacitor within a defined surface area of the integrated circuit. The third technique is to use a material having a high dielectric constant for the dielectric.
Unfortunately, the first technique may produce problems because the reliability of device may deteriorate when using dielectric films of 100 .ANG.ngstroms or less in thickness, due to the generation of Fowler-Nordheim tunneling currents. The second technique may involve the formation of three-dimensional capacitor structures which may complicate the fabrication processes.
The third technique of using a material having a high dielectric constant for the capacitor dielectric has also been widely investigated. In particular, dielectric films formed using a ferroelectric material have been proposed. Ferroelectric materials include oxides of a Perovskite structure having a high dielectric constant, such as PbZrTiO.sub.3 (PZT) or BaSrTiO.sub.3 (BST). A ferroelectric material has a spontaneous polarization phenomenon, unlike a conventional dielectric film such as a silicon oxide film, a silicon nitride film or a tantalum oxide (Ta.sub.2 O.sub.5) film, and a high dielectric constant of hundreds to approximately 1,000 in a bulk state. Thus, a dielectric film of a ferroelectric material which is 500 .ANG. or more in thickness can be equivalent to an oxide thickness of 10 .ANG. or less.
However, in order to use a ferroelectric material as the dielectric film of a capacitor, the electrode material formed on and under the dielectric film (i.e., the upper and lower electrode materials) may become important. The following conditions should be met for an electrode material of a capacitor using a ferroelectric material. First, a film of a Perovskite structure should be able to be formed on the electrode. Second, a low dielectric film should not be formed on an interface between the electrode and the ferroelectric film. Third, silicon or components of the ferroelectric material should not mutually diffuse. Fourth, the electrode should be easy to pattern. It has been found that platinum group metals having oxidation-resistance and high conductivity, including Platinum (Pt), Ruthenium (Ru) or Iridium (Ir), or conductive oxides such as IrO.sub.2 or RuO.sub.2, can be used for electrodes of a ferroelectric capacitor.
Integrated circuit memory devices generally include a cell region and a periphery region in an integrated circuit substrate. In a memory device including a conventional capacitor, which uses an oxide/nitride/oxide (ONO) film as the dielectric film and electrodes formed of polysilicon, resistors in the periphery region are also generally formed of the material which forms the upper electrode of the capacitor. Unfortunately, in a ferroelectric capacitor including an upper electrode formed of the platinum group metals or an oxide thereof, the resistance of the electrode may be excessively low. Thus, the upper electrode of the capacitor generally cannot be used as the resistor of the periphery region.
In general, resistors are used for a voltage generator and an RC delay in the periphery region, which generally require a resistance of several k .OMEGA.. When the desired resistance is low, the resistor of the periphery region is generally formed of the polysilicon used for gate electrodes of a cell region. When the desired resistance is high, it is generally formed of the polysilicon used for an upper electrode of the capacitor. However, when the memory device is integrated on the order of several gigabytes, formation of the resistor may be limited, when ferroelectric material such as BST or PZT is used for the dielectric film of the capacitor, and the platinum group metals or conductive oxides are used for the electrodes of the capacitor, since it may be difficult to obtain a sufficient resistance. Also, since for the gate electrode of a highly integrated memory device, a structure having low resistance such as a tungsten/silicide (WSi.sub.x) structure or a titanium silicide (TiSi.sub.x)/polysilicon structure is generally used, it may also be difficult to obtain a sufficient resistance.
In Table 1, sheet resistances of electrode material of the capacitor having ferroelectric material and gate electrode material are shown.
TABLE 1 ______________________________________ ELECTRODE SHEET SHEET MATERIAL RESISTANCE GATE MATERIAL RESISTANCE (1500 .ANG.) (.OMEGA./.quadrature.) (1500 .ANG.) (.OMEGA./.quadrature.) ______________________________________ Platinum (Pt) 0.71 WSi.sub.x /poly-Si 6-7 Iridium (Ir) 0.34 TiSi.sub.x /poly-Si 2-3 Ruthenium (Ru) 0.49 poly-Si about 100 ______________________________________
As shown in Table 1, the sheet resistance of gate electrodes having a structure of a low resistance or the upper electrode may be excessively low. Accordingly, when the materials are used for a resistor of the periphery region, the necessary length of the resistor may make it difficult to integrate. For example, if 1 .mu.m of resistor width is used, in order to form a resistor of 1 k .OMEGA., polysilicon having a sheet resistance of 100 .OMEGA./.quadrature. generally requires a length of 10 .mu.m. WSi.sub.x /polysilicon having a sheet resistance of 2 .OMEGA./.quadrature. generally requires a length of 500 .mu.m. Thus, the resistor may occupy much of the periphery region. Also, when platinum is used for the upper electrode of the ferroelectric capacitor, the upper electrode of the capacitor generally cannot be used for the resistor of the periphery region.
Referring to FIGS. 1 through 3B, fabricating methods for conventional ferroelectric capacitors will be described. FIG. 1 is a cross-sectional view illustrating a first conventional method for forming a capacitor having a ferroelectric material, which is described in an article entitled "A Memory Cell Capacitor With Ba.sub.x Sr.sub.1-x TiO.sub.3 (BST) Film for Advanced DRAMs" to Ohno et al., 1994 Symposium on VLSI Technology Digest of Technical Papers, pp. 149-150.
Referring to FIG. 1, the capacitor has a structure of a Pt lower electrode 2, a BST dielectric layer 4 and a Pt upper electrode 6. However, since Pt has a low sheet resistance, the upper electrode 6 generally cannot be used for the resistor of the periphery region. However, adhesion of the platinum 6 of the upper electrode to an aluminum film 8 of an interconnection layer formed on the platinum layer 6 is generally poor.
FIG. 2 is a cross-sectional view illustrating a second conventional manufacturing method of a capacitor having a ferroelectric material, described in U.S. Pat. No. 5,005,102 to Larson entitled "Multilayer Electrodes for Integrated Circuit Capacitors". In FIG. 2, a method of forming a multilayered upper electrode is shown. As shown in FIG. 2, a conductive barrier layer 17 is inserted between an upper electrode 16 and an interconnection metal layer 18. Compared to the structure shown in FIG. 1, the structure shown in FIG. 2 may have an advantage in that the adhesive characteristic of the upper electrode 16 to the interconnection metal layer 18 is enhanced. The structure may have a disadvantage in that the upper electrode of the capacitor generally cannot be used as a resistor of the periphery region. Reference numeral 12 denotes a lower electrode, and reference numeral 13 denotes an adhesion/barrier layer for enhancing adhesion and preventing mutual reaction between the lower electrode 12 to a dielectric film 14.
FIG. 3A is a cross-sectional view illustrating a third conventional manufacturing method of a capacitor having a ferroelectric material described in Japanese Patent JP6-125057. Between a platinum layer 36 and an aluminum layer 38 of an interconnection metal layer, a metal layer 37a having a high melting point such as titanium nitride (TiN) and tungsten-titanium (TiW) is inserted, to thereby prevent mutual diffusion of Al and Pt. Reference numeral 32 denotes a lower electrode and reference numeral 34 denotes a dielectric film.
FIG. 3B is a cross-sectional view illustrating a fourth conventional fabricating method of a ferroelectric capacitor, as described in U.S. Pat. No. 4,982,309 to Shepherd, entitled "Electrodes for Electrical Ceramic Oxide Devices". Between conductive oxide electrode 36 and a metal interconnection layer 38, a barrier layer 37b formed of a metal such as Ruthenium or Iridium, is inserted. Reference numeral 32 denotes a lower electrode and reference numeral 34 denotes a dielectric film.
Referring to FIGS. 3A and 3B, the upper electrode of the capacitor generally cannot be used for a resistor of a periphery region like in FIGS. 1 and 2. Also, in the case of FIG. 3A, the upper electrode, formed of platinum 36 and a metal layer 37a having a high melting point, contacts an interlayer insulating film (not shown), which is generally silicon oxide such as Borophosphorus Silicate Glass (BPSG) or Undoped Silicate Glass (USG). Accordingly, thermal treating at 600.degree. C. or higher after the capacitor formation generally causes reaction of BPSG and TiN. The reaction of BPSG and TiN may generate stress, which may thereby deteriorate the characteristics of the capacitor, as disclosed in Kwon et al., "Degradation-Free Ta.sub.2 O.sub.5 Capacitor After BPSG Reflow at 850.degree. C. for High Density DRAMs", IEDM 93, 1993, pp. 53-56.